FIG. 1 shows a configuration of a conventionally well-known image display system 200. This image display system 200 comprises a reproducer 210 for outputting analog image data Van and a display 220 for displaying an image due to the image data Van output from this reproducer 210.
In the reproducer 210, a decoding section 211 decodes encoded image data reproduced from a recording medium, not shown, such as an optical disc and a digital-to-analog (D/A) converter 212 converts digital image data obtained by this decoding to analog data, thereby obtaining analog image data Van. It is to be noted that the display 220 may be, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc.
However, there is a danger that illegal copy may be performed by utilizing the analog image data Van output from the reproducer 210 in such an image display system 200.
That is, the analog image data Van is converted by an analog-to-digital (A/D) converter 231 into digital image data Vdg, which is supplied to an encoding section 232. In the encoding section 232, the digital image data Vdg is encoded to obtain encoded image data Vcd. Then, this encoded image data Vcd is supplied to a recording section 233 and recorded on a recording medium such as an optical disc.
Conventionally, to prevent illegal copy by use of such analog image data Van, it has been proposed in, for example, Japanese Patent Application Publication No. 2001-245270 etc. that the analog image data Van, if its copyright is protected, is scrambled and then output or forbidden from being output.
Although illegal copy can be prevented by outputting the analog image data Van in a condition where it is scrambled or by forbidding it from being output, there may occur a problem that a normal image is not displayed on the display 220.
It has been also proposed conventionally in Japanese Patent Application Publication No. Hei 10-289522 etc. that by providing a noise information generation section to either one or both of a compression decoding section on the reproduction side and a compression decoding section on the recording side and embedding noise information into digital video data to such an extent that single processing is not enough to identify the information in reproduction of an image, the image may be significantly deteriorated when copy is repeated a plurality of number of times although copy itself is possible, thereby substantially limiting the number of times of performing copy.
It is also known conventionally in, for example, Japanese Patent Application Publication No. Hei 07-123271 etc. that encoding is performed by using orthogonal transformation such as discrete cosine transform (DCT). FIG. 2 shows a configuration of an encoding apparatus 300 that uses DCT as orthogonal transformation.
A digital image signal Va received at a receiving terminal 301 is supplied to a blocking circuit 302. This blocking circuit 302 divides the image signal Va on an effective screen into blocks, each of which has a size of, for example, (4×4) pixels.
Data of each of the blocks obtained by the blocking circuit 302 is supplied to a DCT circuit 303. This DCT circuit 303 performs DCT on pixel data of each of the blocks for each block, to obtain coefficient data as a conversion coefficient. This coefficient data is supplied to a quantization circuit 304.
The quantization circuit 304 quantizes coefficient data of each of the blocks by using a quantization table, not shown, to obtain quantization coefficient data of the blocks sequentially. This quantization coefficient data of the blocks is supplied to an entropy encoding circuit 305. This encoding circuit 305 performs, for example, Huffman encoding on quantization coefficient data of the blocks. A Huffman-encoded signal of each of the blocks output from this encoding circuit 305 is output to an output terminal 306 as an encoded digital image signal Vb.
FIG. 3 shows a configuration of a decoding apparatus 320, which corresponds to the above-described encoding apparatus 300.
The encoded digital image signal Vb received at a receiving terminal 321 is supplied to an entropy decoding circuit 322. This image signal Vb is an entropy encoded signal, for example, a Huffman-encoded signal. The decoding circuit 322 decodes the image signal Vb, to obtain quantization coefficient data of each of the blocks.
This quantization coefficient data of each of the blocks is supplied to an inverse quantization circuit 323. The inverse quantization circuit 323 performs inverse quantization on the quantization coefficient data of each of the blocks, to obtain coefficient data of each of the blocks. This coefficient data of each of the blocks is supplied to an inverse DCT circuit 324. The inverse DCT circuit 324 performs inverse DCT on the coefficient data of the blocks for each of them, to obtain pixel data of each of the blocks.
The pixel data of the blocks thus obtained by the inverse DCT circuit 324 is supplied to a deblocking circuit 325. This deblocking circuit 325 brings back its data order to a raster scan order. Thus, from the deblocking circuit 325, a decoded digital image signal Va′ is obtained and output to an output terminal 326.
If noise information is to be embedded by a compression decoding section on the reproduction side or by a compression encoding section on the recording side, a noise information generation section and a circuit to embed the noise information are required, thus bringing about a problem of an increase in circuit scale.
If encoding and decoding that involve orthogonal transformation is to be performed, on the other hand, quantization and inverse quantization are required, thus deteriorating image data. However, in this case, the second or later encoding and decoding is accompanied by no remarkable deterioration in a decoded digital image signal, so that it is impossible to prevent the above-described illegal copy by use of the analog image signal Van.
As one of the encoding approaches, adaptive dynamic range coding (ADRC) has been known in Japanese Patent Application Publication No. Sho 61-144989 etc. By ADRC, only redundancy in a direction of a level of image data is removed by utilizing a space-time correlation, to leave redundancy of the space-time so that concealing may be possible.
FIG. 4 shows a configuration of an encoding apparatus 400 for ADRC encoding.
Digital image data Vc received at a receiving terminal 401 is supplied to a blocking circuit 402. This blocking circuit 402 divides the image data Vc on the effective screen into blocks, each of which has a size of, for example, 4×4 pixels.
Data of images divided into blocks by the blocking circuit 402 is supplied to a maximum value detection circuit 403 and a minimum value detection circuit 404. The maximum value detection circuit 403 detects a maximum value MAX of the image data for each of the blocks. The minimum value detection circuit 404 detects a minimum value MIN of the image data for each of the blocks. The maximum value MAX and the minimum value MIN detected by the detection circuits 403 and 404 respectively are supplied to a subtracter 405. This subtracter 405 performs an operation of dynamic range DR=MAX-MIN.
Further, each block's image data output from the blocking circuit 402 is time-adjusted by a delay circuit 406 and then supplied to a subtracter 407. This subtracter 407 is supplied with a minimum value MIN detected by the minimum value detection circuit 404. This subtracter 407 subtracts, for each block, its minimum value MIN from its image data of the block to obtain minimum value-removed data PDI.
The minimum value-removed data PDI of each block obtained by the subtracter 407 is supplied to a quantization circuit 408. This quantization circuit 408 is supplied with a dynamic range DR obtained by the subtracter 405. This quantization circuit 408 quantizes the minimum value-removed data PDI by using a quantization step determined in accordance with the dynamic range DR. That is, if the number of quantization bits is n, the quantization circuit 408 sets level ranges obtained by equally dividing a dynamic range DR between a maximum value MAX and a minimum value MIN by 2n so that an n-bit code signal may be assigned in accordance with which one of the level ranges the minimum value-removed data PDI belongs to.
FIG. 5 shows a case where the number of quantization bits is 3, in which a dynamic range DR between a maximum value MAX and a minimum value MIN is divided into eight equal level ranges and three-bit code signals (000) through (111) are assigned in accordance with which one of the level ranges the minimum value-removed data PDI belongs to. In FIG. 5, th1 through th7 are each a threshold value that indicates a boundary between the level ranges.
Referring back to FIG. 4, a code signal DT obtained by the quantization circuit 408 is supplied to a data synthesis circuit 411. This data synthesis circuit 411 is supplied with a dynamic range DR obtained by the subtracter 405 after it is time-adjusted by the delay circuit 409 and also with a minimum value MIN detected by the minimum value detection circuit 404 after it is time-adjusted by the delay circuit 410. This data synthesis circuit 411, for each block, synthesizes a minimum value MIN, a dynamic range DR, and a code signal DT having a length as much as the number of pixels in the block, to generate block data. The block data of each block generated by this data synthesis circuit 411 is sequentially output to an output terminal 412 as encoded image data Vd.
FIG. 6 shows a configuration of a decoding apparatus 420, which corresponds to the above-described encoding apparatus 400.
The encoded image data Vd received at a receiving terminal 421 is supplied to a data disassembly circuit 422, where it is disassembled into a minimum value MIN, a dynamic range DR, and a code signal DT of each block.
The code signal DT of each block output from the data disassembly circuit 422 is supplied to an inverse quantization circuit 423. This inverse quantization circuit 423 is supplied also with the dynamic range DR output from the data disassembly circuit 422. In the inverse quantization circuit 423, the code signal DT of each block is inverse-quantized in accordance with the dynamic range DR of the corresponding block, to obtain a minimum value-removed data PDI′.
In this case, as shown in FIG. 5, the dynamic range DR is equally divided by the number of quantization bits, so that mid-values L1 to L8 of the ranges are utilized as decoded values (minimum value-removed data PDI′) of the code signals DT.
The minimum value-removed data PDI′ of each block obtained by the inverse quantization circuit 423 is supplied to an adder 424. This adder 424 is also supplied with the minimum value MIN output from the data disassembly circuit 422. The adder 424 adds the minimum value MIN to the minimum value-removed data PDI′, to obtain image data.
The image data of each block obtained by this adder 424 is supplied to a deblocking circuit 425. The deblocking circuit 425 brings back the data order to its raster scan order. Thus, decoded image data Vc′ is obtained from the deblocking circuit 425. This image data Vc′ is output to an output terminal 426.
In the case of encoding by use of the above-described conventional ADRC method, as shown in FIG. 5, a dynamic range DR′ after inverse quantization is smaller than a dynamic range DR before quantization, so that the image data is deteriorated. However, this deterioration is not so significant.